DFT (Design For Test) Lead (6251)
itd • Arizona
Posted: July 24, 2026
Job Description
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration.
Location: Hybrid in Carlsbad, CA or Allentown, PA, or U.S. Remote. Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST).
Duration: 14 months
We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship.
Responsibilities:
- Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging.
- Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs.
- Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures.
- Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability.
- Collaborate with physical design, validation, and hardware engineering teams throughout the complete silicon product lifecycle.
- Design, validate, and release ATPG patterns while supporting manufacturing test readiness and production ramp.
- Develop technical solutions and resolve complex DFT challenges with minimal supervision while providing technical leadership to the broader engineering team.
Internal Responsibilities:
- Attend regular internal practice community meetings.
- Collaborate with your itD practice team on industry thought leadership.
- Complete client case studies and learning material (blogs, media material).
- Build out material to contribute to the Digital Transformation practice.
- Attend internal itD networking events (in person and virtual).
- Work with leadership on career fast-track opportunities.
Required Qualifications and Skills:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8–10+ years of ASIC Design-for-Test (DFT) engineering experience.
- Hands-on experience implementing JTAG protocols, scan architectures, memory BIST (MBIST), BISR, boundary scan, and integration of third-party IP and high-speed digital/analog macros.
- Experience with ATPG methodologies and industry-standard EDA tools, including Tessent, Xcelium, Genus, and Tempus or PrimeTime.
- Hands-on experience with at least one full project involving post-silicon debug of DFT patterns, including scan, MBIST, boundary scan, and production release.
- Strong understanding of ASIC design, silicon validation, and test methodologies.
- Demonstrated ability to independently develop technical solutions and troubleshoot complex DFT issues.
Preferred Qualifications and Skills:
- Experience developing and standardizing DFT methodologies from design through high-volume manufacturing.
- Ability to mentor and train engineering teams on DFT best practices.
- Strong communication and presentation skills.
- Excellent analytical and problem-solving abilities with strong attention to detail.
- System-level understanding of networking and photonic solutions.
- Ability to quickly learn new technologies and adapt within a fast-paced engineering environment.
Education:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field required. Master's degree preferred.
Additional Content
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration.
Location: Hybrid in Carlsbad, CA or Allentown, PA, or U.S. Remote. Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST).
Duration: 14 months
We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship.
Responsibilities:
- Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging.
- Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs.
- Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures.
- Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability.
- Collaborate with physical design, validation, and hardware engineering teams throughout the complete silicon product lifecycle.
- Design, validate, and release ATPG patterns while supporting manufacturing test readiness and production ramp.
- Develop technical solutions and resolve complex DFT challenges with minimal supervision while providing technical leadership to the broader engineering team.
Internal Responsibilities:
- Attend regular internal practice community meetings.
- Collaborate with your itD practice team on industry thought leadership.
- Complete client case studies and learning material (blogs, media material).
- Build out material to contribute to the Digital Transformation practice.
- Attend internal itD networking events (in person and virtual).
- Work with leadership on career fast-track opportunities.
Required Qualifications and Skills:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8–10+ years of ASIC Design-for-Test (DFT) engineering experience.
- Hands-on experience implementing JTAG protocols, scan architectures, memory BIST (MBIST), BISR, boundary scan, and integration of third-party IP and high-speed digital/analog macros.
- Experience with ATPG methodologies and industry-standard EDA tools, including Tessent, Xcelium, Genus, and Tempus or PrimeTime.
- Hands-on experience with at least one full project involving post-silicon debug of DFT patterns, including scan, MBIST, boundary scan, and production release.
- Strong understanding of ASIC design, silicon validation, and test methodologies.
- Demonstrated ability to independently develop technical solutions and troubleshoot complex DFT issues.
Preferred Qualifications and Skills:
- Experience developing and standardizing DFT methodologies from design through high-volume manufacturing.
- Ability to mentor and train engineering teams on DFT best practices.
- Strong communication and presentation skills.
- Excellent analytical and problem-solving abilities with strong attention to detail.
- System-level understanding of networking and photonic solutions.
- Ability to quickly learn new technologies and adapt within a fast-paced engineering environment.
Education:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field required. Master's degree preferred.