Sr. EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning

Description

• Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today’s AI workloads in datacenters all around the world. As a Sr. EMIR Engineer, you’ll contribute

Description

• Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today’s AI workloads in datacenters all around the world. As a Sr. EMIR Engineer, you’ll contribute to the EMIR sign-off of our SoCs and help maintain a high bar on quality. We’re searching for an experienced EMIR engineer with a proven track record of handling challenges at scale. In this role, you’ll be working directly with architects, designers, verification engineers, power integrity engineers and physical design experts - defining best practices in power grid design, developing test cases & vectors to model demand currents accurately, modeling & signing-off EMIR taking into account board and package impact, advancing the state-of-the-art in EMIR analysis and modeling. Key job responsibilities * Design & analyze power grids * Setup flows for EMIR analysis * Run EMIR analysis for large subsystems, SoCs * Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis * Develop and maintain dashboards for EMIR rollups * Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation A day in the life Depending on the state of the project, you may find yourself working on the following: * Design and evaluate power grids * Working with designers, architects and verification engineers to come up with worst-case vectors for power and IR analysis * Root cause causes of low annotation or low switching coverage with vectors * Develop & maintain dashboards to track EMIR status * Root cause causes of IR drop and suggest solutions to fix * Combine IR analysis of SoC with IR at board and package level (concurrent IR analysis) * Do post-silicon power measurements and correlate with simulation. * Innovate on ways to model VR, board and package impact on voltage drop more accurately. * Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis About the team We are a start-up like team where no-one says "this is not my job" and you won't find anyone telling you to stay in your lane. This is a fast-paced, intellectually challenging position, and you’ll work with thought-leaders in multiple technology areas. We encourage collaboration and teamwork with multiple teams and engineers including architects, RTL designers, Verification engineers, , Physical Design engineers, Emulation engineers and software engineers.

Basic Qualifications

• - 5+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS - Expert on EMIR analysis tools like Redhawk-SC or Voltus or similar - Deep, circuit-level understanding of power, EM and IR - Ability to give feedback to RTL designers and Physical Designers on how to reduce IR - Highly proficient with scripting language (Tcl, Perl, Python or similar) - Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level

Preferred Qualifications